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Those of us who are familiar with technology are more or less conditioned to acknowledge and even anticipate change as a natural part of the course of things. Fresh gadgets and gizmos debut on a regular basis, each one presenting some set of advantages or refinements over the previous generation. (The Ultimate Desktop Replacement Laptop, Feb2009)
The Core i7 modifies the setting quite a bit, but much of what you require to know about it is evident in the picture of the processor die below, with the major components labeled.
What you’re considering, by the way, is a pretty good-sized chip—an estimated 731 million transistors set into a 263 mm² area via the same 45nm, high-k fabrication process used to generate "Penryn" Core 2 chips. Penryn has roughly 410 million transistors and a die area of 107 mm², but obviously, it takes two Penryn dies to make a single quad-core product. Meanwhile, AMD’s native quad-core Phenom chips have 463 million transistors but engage a larger die area of 283 mm² since they’re made on a 65nm process and have an advanced ratio of (less dense) logic to (denser) cache transistors. Then again, size is to some degree relative; the GeForce GTX 280 GPU is over double the size of a Core i7 or Phenom. (The Ultimate Desktop Replacement Laptop, Feb2009)
Nehalem’s four cores are readily obvious across the hub of the chip, as are the other components (Intel calls these, collectively, the "uncore") in the region of the periphery. The uncore occupies a considerable portion of the die area, most of which goes to the big, shared L3 cache.
This L3 cache is the final level of a basically reworked cache hierarchy. Inside of every core is a 32 kB L1 instruction cache, a 32 kB L1 data cache (it’s 8-way set associative), and a dedicated 256 kB L2 cache (also 8-way set associative). On the outer surface of the cores is the L3, which is much larger at 8 MB and more intelligent (16-way associative) than the L2s. This fundamental arrangement may be recognizable from AMD’s native quad-core Phenom processors, and as with the Phenom, the Core i7′s L3 cache serves as the key means of passing data between its four cores. The Core i7′s cache setup differs from the Phenom’s in key compliments, though, including the detail that it’s inclusive—that is, it replicates the contents of the higher level caches—and functions at higher clock frequencies. As a product of these and other design differences, mas well as a revamped TLB hierarchy, the Core i7′s cache latencies are much lower than the Phenom’s, albeit its L3 cache is four times the size. (Ferguson, 2008)
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